廣州做蛋糕的網(wǎng)站推廣策略可以分為哪三種
（1）BCD8421碼：十進制數(shù)字轉(zhuǎn)換成BCD8421碼的方法
- 補零：你需要顯示多少位數(shù)字，就在前面補上四倍的位寬。比如你要顯示一個十進制8位的數(shù)字，就在前面補上8*4=32個零。
- 判斷：判斷補零部分顯示的十進制數(shù)字，每位是否大于4，如果大于，則執(zhí)行加3的操作。
- 判斷完成后，向左移位一位。
- 最終位移次數(shù)與十進制數(shù)字位寬相同
（2）Verilog代碼實現(xiàn)：
（3）仿真代碼：
`timescale 1ns/1nsmodule BCD_8421_32_tb;reg clk ;
reg [31:0] data ;
reg reset_n ;wire [3:0] unit ;
wire [3:0] ten ;
wire [3:0] hun ;
wire [3:0] tho ;
wire [3:0] t_tho ;
wire [3:0] h_tho ;
wire [3:0] o_tho ;
wire [3:0] t_o_tho ;initial clk = 1'd1 ;
always #10 clk= ~clk ;initial beginreset_n <= 1'd0;#15;reset_n <= 1'd1;data <= 32'd1234_5678;#30000;data <= 32'd9874_5612;#30000;$stop;
endBCD_8421_32 BCD_8421_32_inst
(.clk (clk ),.data (data ),.reset_n (reset_n ),.unit (unit ),.ten (ten ),.hun (hun ),.tho (tho ),.t_tho (t_tho ),.h_tho (h_tho ),.o_tho (o_tho ),.t_o_tho (t_o_tho ));endmodule
（4）仿真波形：
(5)頂層設(shè)計：
module freq_meter_top
(input clk ,input reset_n ,input clk_test ,output DIO ,output SCLK ,output RCLK
);wire [31:0] freq ;wire [31:0] data ;wire [3:0] unit ;wire [3:0] ten ;wire [3:0] hun ;wire [3:0] tho ;wire [3:0] t_tho ;wire [3:0] h_tho ;wire [3:0] o_tho ;wire [3:0] t_o_tho ;freq_meter_calc freq_meter_calc_inst0
(.clk (clk ) ,.reset_n (reset_n ) ,.clk_test (clk_test) ,.freq (freq )
);BCD_8421_32 BCD_8421_32_inst0
(.clk (clk ),.data (freq ),.reset_n (reset_n ),.unit (unit ),.ten (ten ),.hun (hun ),.tho (tho ),.t_tho (t_tho ),.h_tho (h_tho ),.o_tho (o_tho ),.t_o_tho (t_o_tho ));assign data = {t_o_tho,o_tho,h_tho,t_tho,tho,hun,ten,unit};hex_top hex_top_inst
(.clk (clk ),.reset_n (reset_n ),.data (data ),.DIO (DIO ),.SCLK (SCLK ),.RCLK (RCLK )
);endmodule
（6）頂層仿真代碼：
`timescale 1ns/1nsmodule freq_meter_top_tb;reg clk ;
reg reset_n ;
reg clk_test ;wire DIO ;
wire SCLK ;
wire RCLK ;initial clk = 1'd1;
always#10 clk = ~clk;initial clk_test = 1'd1;
always#100 clk_test = ~clk_test;initial begin reset_n <= 1'd0;#15;reset_n <= 1'd1;#2_000_000;$stop;
endfreq_meter_top freq_meter_top_inst
(.clk (clk ),.reset_n (reset_n ),.clk_test (clk_test),.DIO (DIO ),.SCLK (SCLK ),.RCLK (RCLK )
);defparam freq_meter_top_inst.freq_meter_calc_inst0.MCNT0 = 27'd74_999;defparam freq_meter_top_inst.freq_meter_calc_inst0.MCNT1 = 27'd12_499;endmodule（7）仿真波形：
（8）引腳分配：
（9）實驗現(xiàn)象：
