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名稱:DDS信號發(fā)生器波形發(fā)生器
軟件:Quartus
語言:VHDL
要求:
在EDA平臺中使用VHDL語言為工具,設(shè)計一個常見信號發(fā)生電路,要求:
1.?能夠產(chǎn)生鋸齒波,方波,三角波,正弦波共四種信號;
2.?信號的頻率和幅度可以通過按鍵調(diào)節(jié);
3.?采用模塊化設(shè)計,包含但不局限于:調(diào)頻模塊,調(diào)幅模塊,波形的選擇與切換模塊等;
代碼下載:DDS信號發(fā)生器波形發(fā)生器VHDL_Verilog/VHDL資源下載
代碼網(wǎng):hdlcode.com
部分代碼展示
LIBRARY?ieee;USE?ieee.std_logic_1164.all; USE?ieee.std_logic_unsigned.all; --DDS頻率等于clk*N/2^13,clk為輸入時鐘,N為頻率控制字frequency;2^13是因為ROM里面存儲了8192個點,相位累加器位寬為13位 ENTITY?DDS_top?ISPORT?(clk_in??????:?IN?STD_LOGIC;--時鐘 rst_p:?IN?STD_LOGIC;--復(fù)位wave_select??:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);--01輸出sin,10輸出方波,11輸出三角波,00鋸齒frequency_key????:?IN?STD_LOGIC;--頻率控制按鍵amplitude_key????:?IN?STD_LOGIC;--幅值控制按鍵 wave?????????:?OUT?STD_LOGIC_VECTOR(15?DOWNTO?0)--輸出波形); END?DDS_top; ARCHITECTURE?behave?OF?DDS_top?IS --例化模塊 --波形選擇模塊COMPONENT?wave_sel?ISPORT?(clk_in??????:?IN?STD_LOGIC;wave_select??:?IN?STD_LOGIC_VECTOR(1?DOWNTO?0);douta_fangbo?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);douta_sanjiao?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);douta_sin????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0); douta_juchi??:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0));END?COMPONENT;--相位累加器模塊COMPONENT?Frequency_ctrl?ISPORT?(clk_in??????:?IN?STD_LOGIC;frequency????:?IN?STD_LOGIC_VECTOR(9?DOWNTO?0);addra????????:?OUT?STD_LOGIC_VECTOR(12?DOWNTO?0));END?COMPONENT; --ROM表 COMPONENT?sin_ROM?IS PORT ( address:?IN?STD_LOGIC_VECTOR?(12?DOWNTO?0); clock:?IN?STD_LOGIC??:=?'1'; q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0) ); END?COMPONENT; --ROM表 COMPONENT?fangbo_ROM?IS PORT ( address:?IN?STD_LOGIC_VECTOR?(12?DOWNTO?0); clock:?IN?STD_LOGIC??:=?'1'; q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0) ); END?COMPONENT; --ROM表 COMPONENT?sanjiao_ROM?IS PORT ( address:?IN?STD_LOGIC_VECTOR?(12?DOWNTO?0); clock:?IN?STD_LOGIC??:=?'1'; q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0) ); END?COMPONENT; --ROM表 COMPONENT?juchi_ROM?IS PORT ( address:?IN?STD_LOGIC_VECTOR?(12?DOWNTO?0); clock:?IN?STD_LOGIC??:=?'1'; q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0) ); END?COMPONENT; --按鍵頻率控制 COMPONENT?Frequency_add?ISPORT?(clk_in????:?IN?STD_LOGIC;rst_p?????:?IN?STD_LOGIC;frequency_key?????:?IN?STD_LOGIC;frequency??:?OUT?STD_LOGIC_VECTOR(9?DOWNTO?0)--頻率控制字,10位位寬,變化范圍可以為1~1000); END?COMPONENT; --按鍵幅值控制 COMPONENT?amplitude_add?ISPORT?(clk_in????:?IN?STD_LOGIC;rst_p?????:?IN?STD_LOGIC;amplitude_key?????:?IN?STD_LOGIC;amplitude??:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--幅值); END?COMPONENT;SIGNAL?addra?????????:?STD_LOGIC_VECTOR(12?DOWNTO?0);SIGNAL?douta_fangbo??:?STD_LOGIC_VECTOR(7?DOWNTO?0);SIGNAL?douta_sanjiao?:?STD_LOGIC_VECTOR(7?DOWNTO?0);SIGNAL?douta_sin?????:?STD_LOGIC_VECTOR(7?DOWNTO?0); SIGNAL?douta_juchi?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);SIGNAL?wave_temp?????????:??STD_LOGIC_VECTOR(7?DOWNTO?0);--波形SIGNAL?frequency????:?STD_LOGIC_VECTOR(9?DOWNTO?0);--頻率控制字,控制輸出波形頻率,值越大,頻率越大SIGNAL?amplitude????:?STD_LOGIC_VECTOR(7?DOWNTO?0);--幅值控制字,值越大,幅值越大 BEGIN --按鍵頻率控制 i_Frequency_add:?Frequency_addPORT?MAP(clk_in????=>?clk_in,rst_p?????=>?rst_p,frequency_key??=>?frequency_key,frequency??=>?frequency--頻率控制字,10位位寬,變化范圍可以為1~1000); --按鍵幅值控制 i_amplitude_add:?amplitude_addPORT?MAP(clk_in????=>?clk_in,rst_p?????=>?rst_p,amplitude_key??=>?amplitude_key,amplitude??=>?amplitude--幅值控制字);--方波ROM,存儲波形數(shù)據(jù)i_fangbo_ROM?:?fangbo_ROMPORT?MAP?(clock???=>?clk_in,address??=>?addra,q??=>?douta_fangbo);--三角波ROM,存儲波形數(shù)據(jù)i_sanjiao_ROM?:?sanjiao_ROMPORT?MAP?(clock???=>?clk_in,address??=>?addra,q??=>?douta_sanjiao);--sin波ROM,存儲波形數(shù)據(jù)i_sin_ROM?:?sin_ROMPORT?MAP?(clock???=>?clk_in,address??=>?addra,q??=>?douta_sin);--鋸齒波ROM,存儲波形數(shù)據(jù)i_juchi_ROM?:?juchi_ROMPORT?MAP?(clock???=>?clk_in,address??=>?addra,q??=>?douta_juchi);--相位累加器i_Frequency_ctrl?:?Frequency_ctrlPORT?MAP?(clk_in????=>?clk_in,frequency??=>?frequency,--頻率控制字addra??????=>?addra--輸出地址);--波形選擇控制i_wave_sel?:?wave_selPORT?MAP?(clk_in????????=>?clk_in,wave_select????=>?wave_select,--01輸出sin,10輸出方波,11輸出三角波douta_fangbo???=>?douta_fangbo,--方波douta_sanjiao??=>?douta_sanjiao,--三角douta_sin??????=>?douta_sin,--正弦 douta_juchi????=>?douta_juchi,--鋸齒wave???????????=>?wave_temp--輸出波形?);wave<=wave_temp*amplitude;--波形乘以幅值 END?behave;
設(shè)計文檔(文檔點擊可下載):
設(shè)計文檔.doc
DDS原理
1. 工程文件
2. 程序文件
ROM IP核
3. 程序編譯
4. RTL圖
5. Testbench
6. 仿真圖
整體仿真圖
相位累加器模塊
波形選擇模塊
正弦波ROM模塊
三角波ROM模塊
方波ROM模塊
鋸齒波ROM模塊
按鍵控制頻率信號模塊
按鍵控制幅值信號模塊