需求：

用兩段式狀態(tài)機(jī)設(shè)計(jì)序列碼檢測(cè)機(jī)。這個(gè)序列碼檢測(cè)機(jī)用于檢索連續(xù)輸入的 1bit 數(shù)據(jù)

（每個(gè)時(shí)鐘周期輸入 1bit），當(dāng)檢測(cè)到一串“101100”的輸入數(shù)據(jù)時(shí)，產(chǎn)生一個(gè)時(shí)鐘周期的

高脈沖指示信號(hào)

狀態(tài)圖

 //實(shí)現(xiàn)狀態(tài)機(jī)切換//101100 //完成切換后，輸出高脈沖`timescale 1ns/1ps
module vlg_design(input i_clk,input i_rest_n,input i_incode,output reg   o_vaild);parameter IDLE = 4'd0; 
parameter S1   = 4'd1; 
parameter S2   = 4'd2; 
parameter S3   = 4'd3; 
parameter S4   = 4'd4; 
parameter S5   = 4'd5; 
parameter S6   = 4'd6; reg [3:0] cstate;
reg [3:0] nstate;always @(posedge i_clk) beginif(!i_rest_n) cstate <= IDLE;else cstate <= nstate;
endalways @(*) begincase(cstate)IDLE:begino_vaild <= 1'd0;if(i_incode == 1) nstate <= S1;else nstate <= IDLE;endS1:begino_vaild <= 1'd0;if(i_incode == 0) nstate <= S2;else nstate <= S1;endS2:begino_vaild <= 1'd0;if(i_incode == 1) nstate <= S3;else nstate <= IDLE;endS3:begino_vaild <= 1'd0;if(i_incode == 1) nstate <= S4;else nstate <= S2;endS4:begino_vaild <= 1'd0;if(i_incode == 0) nstate <= S5;else nstate <= S1;endS5:begino_vaild <= 1'd0;if(i_incode == 0) nstate <= S6;else nstate <= S3;endS6:begino_vaild <= 1'd1;if(i_incode == 1) nstate <= S1;else nstate <= IDLE;end        default :beginnstate <= IDLE;o_vaild <= 1'd0;endendcase
endendmodule

`timescale 1ns/1psmodule testbench_top();//參數(shù)定義`define CLK_PERIORD        20        //時(shí)鐘周期設(shè)置為20ns（50MHz）    //接口申明
reg i_clk;
reg i_rest_n;
reg i_incode;
wire o_vaild;//對(duì)被測(cè)試的設(shè)計(jì)進(jìn)行例化vlg_design        uut_vlg_design(.i_clk(i_clk),.i_rest_n(i_rest_n),.i_incode(i_incode),.o_vaild(o_vaild) );    ///initial begini_clk <= 0;
i_rest_n <= 0;
#20;
i_rest_n <= 1;endalways #(`CLK_PERIORD/2) i_clk = ~i_clk;
integer i;initial begin@(posedge i_clk);
@(posedge i_rest_n);my_task(6'b101100);
my_task(6'b101100);my_task(6'b111100);
my_task(6'b101110);
my_task(6'b101100);
repeat(10)@(posedge i_clk);#2_000_000;
$stop;
endtask my_task;  input [5:0] data;    begin  for(i=0;i < 6;i = i+1) begini_incode <= data[5-i];@(posedge i_clk);endend  
endtaskendmodule

仿真波形